TAPR1.4

From: KC6HPN @ WB6YMH.#SOCA.CA

TAPR FULL-DUPLEX (NEW) 9600 BAUD MODEM MODS BY KC6HPN  (PART 3 OF 4)

If the input signal to a flip-flop is in transition when the flip-flop is
clocked, the flip-flop will briefly become metastable.  That is, its output
will hover between logic 0 and logic 1.  In a short period, the flip-flop will
resolve the metastable state and settle to a 1 or a 0.  Two identical flip-
flops connected to in PARALLEL to the same asynchronous input (as are U7B and
U16) may not only produce glitches on their outputs, but will often settle to
DIFFERENT logic states.   Ooops!  Half the modem thinks it sees the bit, half
doesn't.  This causes bit errors and faulty DCD.

What the double-buffer  does is this: 1. On the first clock edge, the first
flip-flop clocks in the asynchronous data and resolves the metastable state.
2. On the second clock, the second flip-flop clocks in the settled data and
provides a stable, glitch-free output.  Propagation delay and setup and hold
time requirements prevent the two flip-flops from clocking the glitchy data
straight through, even though they are using the same clock edge.

A deglitched, synchronous output is then passed to U16 for DCD and bit clock
generation, and to U7B for bit recovery.  Glitches formerly generated in U7B
by metastability and passed to U19F through U11D are eliminated, removing the
need for a (bad) glitch filter formed by R34 and C24.

This circuit improved both DCD reliability and data recovery considerably on
my modem.  If your DCD indicator (on the modem) flickers even during a strong
signal and you get many retries, this circuit will help.

    HOW: The general method is to construct a circuit assembly using an IC
socket and mount the assembly "dead bug" style (upside-down) in the vacant U6
space.  If you are using the optional internal clock generator and U6 is
present, use any other convenient location.  Once assembled and connected, the
assembly is secured to the modem PC board by double-backed tape.
CONTINUED IN TAPR1.5